Monday, October 25, 2010

[FREE-FOOD] Fwd: Stanford IEEE Presents: Prof. Mark Horowitz - Trends in VLSI Design Automation

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Subject: Stanford IEEE Presents: Prof. Mark Horowitz - Trends in VLSI Design Automation
Date: Mon, 25 Oct 2010 08:51:05 -0700
From: Frank Austin Nothaft <>

Stanford IEEE Presents...

Trends in VLSI Design Automation
Mark Horowitz, Yahoo Founder's Professor, Chair of the Department of Electrical Engineering
October 26, 2010, 5:00 to 6:00 PM, CISX 101

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The slowing performance gains from CMOS scaling and the rising design
costs are making it more difficult to continue to deliver value to our
customers. To buck this trend, we need to make design much more
efficient. In many ways our current situation is reminiscent of the
situation in the mid 80's where chips were custom designed, and only
created by chip companies.

Synthesis and placement/routing systems created the ASIC market, and we
need a similar scale improvement today. For many reasons I don't believe
that either the current SoC, or high-level language effort will succeed in
solving this problem.  Instead, we should acknowledge that working out the
interactions in a complex design is complex, and will cost a lot of money,
even when we do it well.  The key is to leverage this work over a broader
class of chips. This approach leads to the idea of building
chip-generators and not chips. That is instead of building a programmable
chip to meet a broad class of application needs, you create a virtual
programmable chip, that is MUCH more flexible than any real chip.  The
application designer (the new chip designer) will then configure this
substrate to optimize their application.  The generator will take this
information and then create the desired chip.  While there are many very
hard problems that need to be addressed to make this work, but none of
them seem insurmountable.  In fact I will provide some recent examples
from my group which indicate the promise of this approach - including
improving the energy efficiency of a H.264 encoder by 200x, and how to
validate a chip generator.

Stanford IEEE Tech Talk - Trends in VLSI Design Automation

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